1. Field of the Invention
This invention relates in general to semiconductor memory device, and more particularly to a structure of a dynamic random access memory (DRAM) cell having a transfer transistor and a tree-type charge storage capacitor.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional memory cell for a DRAM device. As shown in the drawing, a DRAM cell is substantially composed of a transfer transistor T and a charge storage capacitor C. A source terminal of the transfer transistor T is connected to a corresponding bit line BL, and a drain terminal thereof is connected to a storage electrode 6 of the charge storage capacitor C. A gate terminal of the transfer transistor T is connected to a corresponding word line WL. An opposing electrode 8 of the capacitor C is connected to a constant power source. A dielectric film 7 is provided between the storage electrode 6 and the opposing electrode 8 of capacitor C.
In the conventional DRAM manufacturing process, substantially two-dimensional capacitors called planar type capacitors are formed for use with the conventional DRAM devices having a storage capacity less than 1 Mb (million bytes). In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on electrodes disposed on the main surface of a semiconductor substrate, so that the main surface is required to have a relatively large area. This type of a memory cell is therefore not suited for a DRAM having a high level of integration. For a high integration DRAM, such as a DRAM with more than 4 Mb of memory, a three-dimensional capacitor structure, called a stacked-type or a trench-type capacitor, has been introduced.
With the stacked-type or trench-type capacitor, it has been possible to obtain a larger memory for a similar surface area. However, to realize a semiconductor device of an even higher level of integration, such as a very-large-scale integration (VLSI) circuit having a capacity of 64 Mb, a capacitor with a simple three-dimensional structure, such as the conventional stacked-type or trench-type, turns out to be insufficient.
One solution for improving the capacitance of a DRAM memory cell storage capacitor is to use the so-called fin-type stacked capacitor, an example of, which is proposed in Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electronic Devices Meeting, pp. 592-595, Dec. 1988. The fin-type stacked capacitor includes electrodes and dielectric films which extend horizontally in a fin shape in a plurality of stacked layers to increase the surface areas of the electrodes. DRAMs having the fin-type stacked capacitor are also disclosed in U.S. Pat. Nos. 5,071,783; 5,126,810; and 5,206,787.
Another solution for improving the capacitance of a memory cell storage capacitor is to use the so-called cylindrical-type stacked capacitor, an example of, which is proposed in Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM," 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend vertically in a cylindrical shape to increase the surface areas of the electrodes. A DRAM having the cylindrical-type stacked capacitor is also disclosed in U.S. Pat. No. 5,077,688.
With the trend toward increased integration density, the size of the DRAM cell in a plane (the surface area it occupies in a plane) must be further reduced. Generally, a reduction in the size of the memory cell leads to a reduction in charge storage capacity (capacitance) of the storage capacitor. Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of alpha-rays is increased. Therefore, there is a need in this field for a new storage capacitor structure which can maintain capacitance, while occupying a smaller surface area of the device, and a suitable method of fabricating the structure.